A typical integrated circuit contains a plurality of metal pathways to provide electrical power for powering the various semiconductor devices comprising the integrated circuit, and to allow these semiconductor devices to share/exchange electrical information. Within integrated circuits, metal layers are stacked on top of one another by using intermetal or “interlayer” dielectrics that insulate the metal layers from each other. Typically, however, each metal layer must form electrical contact to an additional metal layer. Metal-layer-to-metal-layer electrical contact is achieved by etching a hole (i.e., a via) in the interlayer dielectric that separates the first and second metal layers, and by filling the resulting hole or via with a metal to create an interconnect as described further below.
The use of copper in place of aluminum as the interconnect material for semiconductor devices has grown in popularity due to copper's lower resistivity. Unlike aluminum, however, copper is highly mobile in silicon dioxide and may, as a result of infiltration of copper atoms into the dielectric, create leakage paths through a device's various dielectric layers. Copper atoms also can cause electrical defects in silicon. Accordingly, as best understood with reference to FIGS. 1A–1C described below, a semiconductor device employing copper interconnects requires the creation of encapsulating barrier layers to prevent deleterious incorporation of copper atoms into the device's various material layers.
FIGS. 1A–C show sequential cross-sectional views of the formation of a conventional copper interconnect 10 (FIG. 1C) through an aperture in a dielectric layer disposed between two copper layers, a first copper layer 11a disposed within a dielectric layer D and a second copper layer 11b. With reference to FIG. 1A, to form the copper interconnect 10, a silicon dioxide interlayer dielectric 13 is deposited over the first copper layer 11a. A first via 15 then is etched in the interlayer dielectric 13 to expose the first copper layer 11a. 
Copper is highly reactive with oxygen and easily forms a surface layer of high resistivity copper oxide when exposed to an oxygen rich atmosphere. Because the first layer 11a is copper, a high resistance copper oxide layer 11a′ can form on the top surface of the first copper layer 11a if the first copper layer 11a is exposed to oxygen or water vapor (e.g., air). This oxidation can occur when the wafers, just having the vias etched therein, are moved from an etch tool to a metallization tool. The copper oxide layer 11a will complete formation once all exposed and unoxidized copper is converted to copper oxide. Accordingly, to minimize the resistance of the copper interconnect 10, the copper oxide layer 11a′ must be removed. Typically the copper oxide layer 11a′ is removed by sputtering the copper oxide layer 11a′ with ions generated within a plasma (i.e., sputter-etching), such as argon ions generated within an argon plasma. The argon ions are accelerated toward the wafer via a negative electric bias imposed on the wafer or on the wafer support. These ions strike the wafer and the copper oxide layer 11a′ at the base of the unfilled via, and eject material from the copper oxide layer 11a′ (including copper immediately beneath the copper oxide) due to momentum transfer between the accelerated argon ions and the copper oxide layer 11a′. 
The ejected material, which includes copper atoms 11a″, coats the interlayer dielectric 13 as shown in FIG. 1A. The copper atoms 11a″ contained in the ejected material can enter the interlayer dielectric 13 and drift therethrough under the influence of an applied electric field (e.g., a device voltage), causing deleterious interconnect-to-interconnect leakage currents (i.e., via-to-via leakage currents). Such deleterious via-to-via leakage currents, however, cannot be avoided in conventional copper interconnects if the copper oxide layer 11a′ is removed. Accordingly, conventional copper interconnects suffer from either a high resistance copper oxide layer 11a′ which is left in place to prevent dielectric degradation induced by copper sputtered directly on the wall of the unfilled via, or copper atom induced degradation in the dielectric which leads to via-to-via leakage currents.
Following removal of the copper oxide layer 11a′, a thin barrier layer 17 (e.g., tantalum, tantalum nitride, titanium nitride, tungsten or tungsten nitride) is deposited over the interlayer dielectric 13 and the first copper layer 11a as shown in FIG. 1B. The barrier layer 17 prevents copper atoms from a subsequently deposited copper layer (namely the second copper layer 11b of FIG. 1C) from incorporating into, and thus degrading, the interlayer dielectric 13.
To complete the conventional copper interconnect 10, the second copper layer 11b is deposited over the barrier layer 17 either conformally or in the form of a copper plug 11b′, as shown in FIG. 1C. A copper “seed” layer (not shown) typically is deposited prior to deposition of the copper plug 11b′. Thus, a conventional copper interconnect 10 consists of the first copper layer 11a “in contact” with the second copper layer 11b through the barrier layer 17.
Because the barrier layer 17 can have a resistivity up to 100 times greater than the resistivity of copper, the barrier layer 17 significantly increases the contact resistance of the interconnect 10 formed between the first copper layer 11a and the second copper layer 11b. Therefore, the significant advantage of copper's lower resistivity is not fully realized due to the presence of barrier layers. The barrier layer 17, however, is required to prevent further incorporation of copper atoms within the interlayer dielectric 13.
In sum, conventional copper interconnects suffer from high resistances due to the presence of barrier layers, and can suffer from via-to-via leakage currents due to sputtered copper atom incorporation in the interlayer dielectric 13 during interconnect formation. Accordingly, a need exists for an improved copper interconnect that does not suffer from either high resistance or via-to-via leakage currents.